The present invention is directed to methods for synthesizing balanced clock trees for an integrated circuit design. More specifically, but without limitation thereto, the present invention is directed to partitioning a clock tree into two clock trees, one for memory devices and another for the remaining devices in the integrated circuit design.
As the number of memories increases in integrated circuit designs, the problem of peak instantaneous power becomes increasingly important. Voltage drop due to the peak power demand from simultaneous switching of a large number of memory devices can result in a malfunction in the operation of the integrated circuit.